Ángel Dieguez – Department of Electronic and Biomedical Engineering, Universitat de Barcelona, Barcelona, Spain
Beyond LED microdisplays, InGaN/GaN microLED arrays are expected to greatly expand the potential applications of nitride semiconductors by offering structured light at the micro- or nanometer scale. Potential applications include chip-based microscopy [1], optical neuromorphic computing, LiFi communications or even optogenetics [2]. For all these applications a large number of pixels and high frequency modulation in combination with high illumination efficiency are essential. This combination can only be achieved when nitride chips are directly bonded to silicon CMOS controller chips.
In this work, we present the design of a CMOS panel in 180nm technology developed by the University of Barcelona [3] in the framework of the European SMILE project [4] to be part of a LED microdisplay. The CMOS panel is able to exploit the capabilities of GaN arrays, producing high speed patterns (up to 9.15 kfps) at high optical intensities (up to 120 uA per pixel and 16 gray levels) with a very high resolution of 1411 PPI (512×512 pixels at 18um pitch). In addition, the panel can operate in pulsed mode, allowing the entire matrix to be switched between the stored image and the off state at 1 MHz. Such a panel has been combined with the corresponding GaN matrix by means of relatively low-temperature indium microbeads in a hybrid combination, to achieve a fully integrated structured micro-illumination light engine with the above-mentioned features. The production of the GaN matrix and the hybrid interconnect has been performed at the Technical University of Braunschweig (Germany) [5].
Figure 1 shows the schematic of the integrated circuit in each pixel of the controller. Four bits for each pixel are stored in 6T SRAM cells. This information is converted into current applied to each LED by four weighted-width transistors (M1-M4). The four transistors, together with the SRAM cells, form a 16-level current DAC that establishes a stable current through the LED. With this circuit, the bias current degradation that occurs with typical circuits used to drive these types of LEDs is avoided. The drive branch also includes a thick oxide transistor (M5) for global enable purposes, which cuts the output current and allows PWM to be used. In addition, the M5 transistor allows cathode (nVLED) voltages of up to 3.2 V. This increases the LED bias voltage range from 1.8 V to 5 V, thus extending the current range from 20 nA to 120 μA for typical GaN technology LEDs. Finally, to calibrate the current, two more transistors (M6 and M7) are added. All the drive circuit elements are embedded in 18×18 μm2, including the 8×8 μm2 contact for the LED anode (Figure 2).
Figure 2: Layout of the 18×18 μm2 driver embedded in each pixel, with the 8×8 μm2 aperture for the hybrid junction in orange.
Figure 3 shows the block diagram of the panel. This structure is repeated four times, controlling up to a 512×512 pixel matrix. To reduce the number of I/O pads, the panel implements a sequential structure that handles 256×256 pixels. The figure shows that data enters the chip via 4 data channels (SerCh0 to SerCh3) and a clock (SerClk) through a 600 Mbps DDR SLVS interface. In addition, the chip has a row scan controller that selects the group of columns to be updated (32 pixels) and another serial interface that is responsible for deserializing the data stream, interleaving it and controlling the write procedure. An enable signal of is also included for the global control of the array. Each array is organized into 2×8 subsets of 128×32 pixels, with the minimum write unit being one row of these subsets (i.e., 32 pixels). Each pixel subset has its column data path and row selection signals.
Power planning includes independent power domains, separating the LED array bias voltages (VLED, nVLED) from the digital electronics (VDD, GND) and the I/O ring. In addition, the feeds are distributed across the chip in a mesh structure even within the pixel array, thus minimizing IR drop effects and homogenizing the voltage across the array.
To achieve the microdisplay, the CMOS wafers were processed to have a suitable termination for the interconnection process with the GaN chip. Figure 4 shows the result after placing Indium balls in each die aperture (detail in the layout in Figure 2, and in the inset in Figure 4). The hybrid assembly was custom packaged and mounted on a socket and PCB for characterization. Finally, an image projected onto a quarter of the functional microdisplay is shown in Figure 5.
Figure 4: 200 mm wafer received from the foundry and processed to arrange the balls for the hybrid interconnect. On the right is a detail of the beads arranged on the die. The CMOS chip measures approximately 1.2 x 1.3 cm2.
The described activity, as mentioned above, was the result of a European Union EIC Transition project (SMILE – Scalable Structured Micro Illumination Light Engines). This project was a continuation of an EIC Pathfinder project (ChipScope) and has continued with an EIC Accelerator project (iSMILE, from the company Qubedot) in a highly competitive process. This is the first case of receiving the entire EIC funding stream, recognizing the market potential of gallium nitride-based microLEDs and microLED displays as structured light sources.
[1] Vilà, A., Moreno, S. and Diéguez, A. (2022), 24-1: Can Light Microscopes Really Be Chip-Sized?. SID Symposium Digest of Technical Papers, 53: 271-274. https://doi.org/10.1002/sdtp.15471
[2] Junge, S., Ricci Signorini, M.E., Al Masri, M. et al. A micro-LED array based platform for spatio-temporal optogenetic control of various cardiac models. Sci Rep 13, 19490 (2023). https://doi.org/10.1038/s41598-023-46149-1
[3] Department of Electronic and Biomedical Engineering, Universitat de Barcelona, Barcelona, Spain. Contact: Prof. Angel Dieguez, angel.dieguez@ub.edu.
[4] SMILE Project, cordis.europa.eu/project/id/952135
[5] Institute of Semiconductor Technology, TU Braunschweig, Germany. Contacto: Prof. Andreas Waag.